The current state of the art of semiconductor development is the mass production of large integrated circuits “IC's” containing several million active components. One type of device fitting this description is a large Field Programmable Gate Array “FPGA.” FPGAs and other devices may operate at speeds of several hundred Megahertz and it is not unusual that these integrated circuits include over a thousand pins that bring high speed signals into and out of the integrated circuit die. With a large number of active internal components switching at high speeds, these devices consume large amounts of power. In a system containing several of these and other circuits it is desirable to have a substrate that is optimized for both density of high speed signal conductors and low resistance power connections.
A drawing of a semiconductor substrate optimized for thousands of high density conductors available for high speed signal routing and both low resistance connections for power is shown in FIG. 1. A semiconductor substrate 25 has a plurality of FPGA dice 27-30 disposed upon its surface. The semiconductor substrate contains a thin conductor layers portion characterized as having a plurality of thin fine-pitch conductors. These fine-pitch conductors are used to make high speed and other signal connections between the multiple FPGA dice 27-30. For the power connections to the FPGA dice, thick conductors and vertical through-holes are utilized. The through-holes, electrically couple thick conductors on the bottom plane of the semiconductor substrate to thick conductors present on multiple layers below the plurality of FPGA dice. Power bus bar structures 80 are in mechanical contact with the thick conductors underneath the semiconductor substrate 25 and are also in electrical contact with these thick conductor layers on the bottom plane of semiconductor substrate 25. Power bus bar structures 80 extend underneath the entire length of the semiconductor substrate. Braided copper edge connectors, not shown in FIG. 1, are connected to the power bus bar structures 80 and are used to couple power signals to the power bus bar structures.
Another drawing of a semiconductor substrate with power bus bar structures is shown in FIG. 2. FIG. 2 contains a semiconductor substrate 25, partial FPGA die 27, coupling capacitors 87-88, Thick conductive metal layer 21, and a plurality of power bus bar structures 81-84. Conductive metal layer 21, which may be made of copper, is shown attached to a silicon portion of semiconductor substrate 25 and may be approximately eight microns thick. Power bus bar structures 81-84, are of sufficiently large cross section in order to supply power to FPGAs 27-30 and are each approximately one millimeter wide by one and one-half millimeters in height. If the power bus bars are soldered to conductive metal layer 21 there is sufficient electrical connection but the physical connection to conductive layer 21 and the semiconductor substrate may be subject to delamination during changes in temperature. For example, the coefficient of thermal linear expansion for power bus bars made of copper is seventeen parts per million per degree Centigrade “ppm/° C.” The same coefficient for silicon is three ppm/° C. If a semiconductor substrate with copper power bus bars two inches in length experiences a change in temperature of one-hundred degrees Centigrade, the copper power bus bars 81-84 would expand approximately thirty five microns more than the semiconductor substrate 25 at each end of the semiconductor substrate. With this disparity, it is likely the thick copper power bus bars soldered to conductive metal layer 21 would separate from the semiconductor body attached to conductive metal layer 21. While soldering of the silicon substrate to the copper bus bars provides sufficient electrical contact, its bonded contact is likely insufficient to withstand linear stresses caused by thermal expansion and contraction of the copper bus bars when subjected to changing temperature. A reliable physical connection is desired while still maintaining robust electrical connection.